Current sharing is required in multiphase power converters in order to ensure that the individual phases of the power converter share currents in a predetermined fashion. Usually the phase currents are equalized, but alternative arrangements are known.
Voltage mode control alone is generally understood as not being sufficient to achieve current sharing because the inductor currents are not explicitly controlled. Imperfect matching between phases of the power-train leads to unmatched inductor currents which seriously impacts converter performance reliability and efficiency.
There are many methods of current sharing in DC-DC conversion. Of these, current sharing methods which measure inductor current in each phase and actively balance the currents using a control loop are popular. Methods of current sharing include the introduction of a current control loop in addition to the voltage control loop. Of these, average and peak current mode control loops are popular choices. However, the bandwidth of the current control loop is a concern. The current loop can only match the impedances of the individual phases up to the current share loop bandwidth, which is typically much less than the control loop bandwidth, but the current share bandwidth needs to be large for high performance control.
Furthermore the voltage and current control loops can interact, which may limit achievable voltage loop bandwidth and cause stability problems. As such, an effective current share scheme involves a trade-off between the high bandwidth requirement for accurate matching of the phases but low bandwidth in order to avoid undesired interactions between the control loops which affects stability and voltage loop performance.
Although current share loops based on current mode control are popular, current measurement accuracy is a concern, and these techniques are difficult to reproduce in digital power controllers because of the demands placed on the current sampling ADC (Analog to Digital Converter).
Accordingly, passive current sharing techniques such as duty cycle matching are desirable as this technique shares the currents between the phases in a manner which minimizes overall power loss associated with resistive phase current imbalance, hence improving efficiency over other current share methods. Additionally, there are no stability concerns arising from the presence of multiple control loops. An example of a two phase duty cycle matching circuit for converting an input voltage (Vi) to an output voltage (Vo) is shown in FIG. 1. In this circuit, each phase is arranged as a buck converter. The buck converter which will be familiar to those skilled in the art, has an inductor L1, L2 which is switchably connected at a first end by a switching arrangement 3a-b, 4a-b to either an input voltage Vi or ground. The opposite ends of the inductors are connected to a common capacitor 8. In the exemplary circuit shown, the buck converter is a synchronous buck converter with each phase employing two switches 3a-b, 4a-b. It will be appreciated that the circuit may also be operated in a non-synchronous form in which the second switch 3b, 4b in each switching arrangement is replaced with a diode. The output voltage Vo is compared to a desired set point 10 and sampled by an Analog to Digital Converter 11 to produce a digital error signal 12. The error signal in turn is fed to a compensator\controller 14. The controller is responsive to the error signal to provide a control signal 16. The controller may for example be a PID controller. The controller may include a low pass filter to reduce the effects of noise. The control signal identifies a value for the duty cycle of the phases. The control signal in turn is supplied to a Digital Pulse Width Modulator (DPWM) 18 which generates switching signals φ1, φ2 for the switching arrangements of the individual phases. In operation, the switching signals for the individual phases are staggered as shown in FIG. 2. The DPWM is trailing edge modulated, so during operation each phase operates at the switching frequency, with their rising edges being 50% out of phase. Thus in the case of the two phase circuit shown in FIG. 2, the duty cycle is set for one phase in one cycle and for the other cycle on the next. As a result the duty cycle of individual phases are not identical. The same duty cycle could be supplied to each phase but this would effectively halve the bandwidth of the controller.
Whilst it might be assumed that best efforts of matching impedances in the power train achieves inherent current matching, this is not the case and in fact in general does not equalize the phase currents, as shown in the experimental results of FIG. 3. It is clear from these experimental results that the current in the inductors of each phase (IL1 and IL2) are not equal and in fact the differences between the currents (IL1−IL2) is quite substantial.
Methods to implement the duty-cycle matching concept have been designed and tested. Although they have performed well, there is some calculation overhead involved in the algorithm of some of these that limits control performance by issuing the same duty cycle to each phase and in others duty cycle matching is only maintained approximately. Techniques that use a loop to keep the duty-cycles matched have associated stability and performance concerns.